Micro Electro Mechanical Systems (MEMS) are used in a wide variety of systems such as accelerometers, gyroscopes, infrared detectors, micro turbines, etc. For high volume applications, fabrication costs may be reduced by monolithic integration of MEMS along with the Complimentary Metal Oxide Semiconductor (CMOS) electronics that are used to drive or control them (driving electronics). In addition, for 2D imaging applications (e.g. detectors, displays), monolithic integration of MEMS and CMOS processing may be advantageous as this simplifies interconnection issues.
An easy approach for monolithic integration is post-processing MEMS on top of driving electronics, as this does not introduce any change into the standard fabrication processes that are used to fabricate the driving electronics. It also allows the realization of a more compact micro-system. This may not be possible if the MEMS-device is produced prior to the formation of the driving electronics. Unfortunately, post processing imposes an upper limit on the fabrication temperature of MEMS to avoid any damage or degradation in the performance of the driving electronics. This upper limit is typically about 450° C. An overview of several approaches with respect to the integration of driving electronics and MEMS devices may be found in “Why CMOS-integrated transducers? A review”, Microsystem Technologies, Vol. 6 (5), p 192-199, 2000, by A. Witvrouw et al.
For many micromachined devices, such as transducers and other freestanding structures, the mechanical properties of the applied thin films may be critical to their success. For example, stress or stress gradients can cause freestanding thin-film structures to warp to the point that these structures become useless. Such thin film layers have ideally a low stress and a zero stress gradient. If the stress is compressive (often denoted by a minus-sign (−)), structures may buckle. If the stress is tensile (often denoted by a plus-sign (+)), structures may break. If the stress gradient is too compressive or tensile, microstructures may deform. For example, cantilevers may bow or under too compressive or tensile a stress.
Polycrystalline silicon (poly Si) has been widely used for MEMS applications. The main disadvantage of this material is that it requires high processing temperatures (above 800° C.) which are above the upper limit described above. These high temperatures are used to achieve the desired physical properties of a MEMS device One such physical property in particular being stress as explained above, and further in “Strain studies in LPCVD polysilicon for surface micromachined devices,” Sensors and Actuators A (physical), A77 (2), p. 133-8 (1999), by J. Singh S. Chandra et al. This incompatibility of processing temperatures means that poly Si MEMS applications cannot be used for integration with CMOS if a CMOS device is processed before a MEMS device.
Polycrystalline silicon germanium (poly SiGe) is known in the art as an alternative to poly Si as they share similar properties. The presence of germanium reduces the melting point of the silicon germanium alloy and hence the desired physical properties may be realized at lower temperatures, allowing the growth on top of a standard CMOS device. Depending on the germanium concentration and the deposition pressure, the transition temperature from amorphous to polycrystalline may be reduced to 450° C., or even lower, compared to 580° C. for CVD poly Si.
In order to use such a poly SiGe layer for a MEMS device (e.g., gyroscopes, accelerometers, micro-mirrors, resonators, etc.), which may be 0.3 μm to 12 μm thick, for example, requires a low-stress (<20 MPa compressive and <100 MPa tensile) and a low electrical resistivity poly SiGe layer. Another important consideration for industrial applicability is that such a poly SiGe layer should be produced with a relatively high deposition rate. In addition, a reasonably small variance of characteristics between different points on the wafer should be achieved.
Fast deposition methods such as PACVD (Plasma Assisted CVD) or PECVD (Plasma Enhanced CVD) having a typical deposition rate >100 nm/min, normally result in amorphous SiGe layers with high stress and high resistivity at temperatures compatible with CMOS (450 degrees C. or lower), for low germanium concentrations. Polycrystalline layers deposited with PECVD with low stress and low resistivity are described in WO 01/74708, but only at higher temperatures.
Slow deposition methods such as CVD (with typical deposition rates of about 5-15 nm/min) can give crystalline layers with low resistivity at 460 degrees C., but this is not an economical process in a single wafer tool for. For example, typical 10 μm thick layers require a long processing time In WO 01/74708, it is indicated that the CVD deposition of in-situ boron doped poly crystalline SiGe at lower temperature (around 400 degrees C.) is feasible if the Ge concentration is high enough (above 70%) and if the boron concentration is high enough (above 1019/cm3). This high Ge concentration does not include the use of a Ge sacrificial layer. In addition, an additional anneal at 450 degrees C. was needed to optimize the mechanical properties of this layer.
The minimum temperature of 450 degrees C. for CVD layers and 550 degrees C. for PECVD layers excludes the possibility of post processing SiGe devices on top of advanced CMOS devices. These advanced CMOS devices may include low-permittivity (low-k) inter-metal dielectrics that have a limited thermal budget. Additionally, processing on top of other (low cost) substrates, such as multi-chip modules or even plastics, it may require SiGe deposition temperatures below 400 degrees C.
Currently, methods like metal-induced crystallization and pulsed laser annealing of SiGe films are under development. However they require a deposition of a seed layer and/or special treatment of the deposited SiGe film in order to achieve the required properties. Therefore, there is a need for a SiGe film that facilitates the integration of CMOS and advanced CMOS devices with micromachined/MEMS devices.